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M28W320CT M28W320CB
32 Mbit (2Mb x16, Boot Block) Low Voltage Flash Memory
PRELIMINARY DATA
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SUPPLY VOLTAGE - VDD = 2.7V to 3.6V: for Program, Erase and Read - VDDQ = 1.65V or 2.7V: Input/Output option - VPP = 12V: optional Supply Voltage for fast Program
BGA
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ACCESS TIME - 2.7V to 3.6V: 90ns - 2.7V to 3.6V: 100ns
TSOP48 (N) 12 x 20mm BGA47 (GB) 8 x 6 solder balls
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PROGRAMMING TIME: - 10s typical - Double Word Programming Option
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PROGRAM/ERASE CONTROLLER (P/E.C.) COMMON FLASH INTERFACE MEMORY BLOCKS - Parameter Blocks (Top or Bottom location) - Main Blocks Figure 1. Logic Diagram
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BLOCK PROTECTION UNPROTECTION - All Blocks protected at Power Up - Any combination of blocks can be protected - WP for block locking
21 A0-A20 W E G RP WP M28W320CT M28W320CB VDD VDDQ VPP 16 DQ0-DQ15
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SECURITY - 64-bit user Programmable OTP cells - 64-bit unique device identifier - One Parameter Block Permanently Lockable
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AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS of DATA RETENTION - Defectivity below 1ppm/year
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VSS
AI03521
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ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Device Code, M28W320CT: 88BAh - Bottom Device Code, M28W320CB: 88BBh
May 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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Figure 2. BGA Connections (Top view through package)
1 2 3 4 5 6 7 8
A
A13
A11
A8
V PP
WP
A19
A7
A4
B
A14
A10
W
RP
A18
A17
A5
A2
C
A15
A12
A9
A20
A6
A3
A1
D
A16
DQ14
DQ5
DQ11
DQ2
DQ8
E
A0
E
VDDQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSS
F
VSS
DQ7
DQ13
DQ4
VDD
DQ10
DQ1
G
AI02686
Figure 3. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 NC A20 W RP VPP WP A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 VDDQ VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
Table 1. Signal Names
A0-A20 DQ0-DQ7 DQ8-DQ15 E G W RP WP VDD VDDQ VPP VSS NC Address Inputs Data Input/Output, Command Inputs Data Input/Output Chip Enable Output Enable Write Enable Reset Write Protect Supply Voltage Power Supply for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Not Connected Internally
12 M28W320CT 37 13 M28W320CB 36
24
25
AI03522
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Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG V IO VDD, VDDQ V PP Parameter Ambient Operating Temperature (2) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage Value -40 to 85 -40 to 125 -55 to 155 -0.6 to VDDQ+0.6 -0.6 to 4.1 -0.6 to 13 Unit C C C V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range.
DESCRIPTION The M28W320C is a 32 Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a Word-byWord basis. The device is offered in the TSOP48 (10 x 20mm) and the BGA47, 0.75mm ball pitch packages. When shipped, all bits of the M28W320C are in the 1 state. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against programming and erase at Power UP. Blocks can be unprotected to make changes in the application and then reprotected. A parameter block "Security Block" can be permanently protected against programming and erase in order to increase the data security. Each block can be programmed and erased over 100,000 cycles. VDDQ allows to drive the I/O pin down to 1.65V. An optional 12V VPP power supply is provided to speed up the program phase at customer production line environment. An internal Command Interface (C.I.) decodes the instructions to access/modify the memory content. The Program/Erase Controller (P/E.C.) automatically executes the algorithms taking care of the timings necessary for program and erase operations. Verification is performed too, unburdening the microcontroller, while the Status Register tracks the status of the operation. The following instructions are executed by the M28W320C: Read Array, Read Electronic Signature, Read Status Register, Clear Status Register, Program, Double Word Program, Block Erase, Program/Erase Suspend, Program/Erase Resume, CFI Query, Block Protect, Block Lock, Block Unprotect, Protection Program. Organisation The M28W320C is organised as 2 Mbit by 16 bits. A0-A20 are the address lines; DQ0-DQ15 are the
Data Input/Output. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. The Program and Erase operations are managed automatically by the P/E.C. Block protection against Program or Erase provides additional data security. Memory Blocks The device features an asymmetrical blocked architecture. The M28W320C has an array of 71 blocks: 8 Parameter Blocks of 4 KWord and 63 Main Blocks of 32 KWord. M28W320CT has the Parameter Blocks at the top of the memory address space while the M28W320CB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Tables 3 and 4. All Blocks are protected at power up. Instruction are provided to protect, unprotect any block in the application. A second register locks the protection status while WP is low (see Block Protection Description). Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. The architecture includes a 128 bits Protection register that are divided into Two 64-bits segment. In the first one, starting from address 81h to 84h, is written a unique device number, while the second one, starting from 85h to 88h, is programmable by the user. The user programmable segment can be permanently protected programming the bit.1 of the Protection Lock Register (see protection register and Security Block). The parameter block (# 0) is a security block. It can be permanently protected by the user programming the bit.2 of the Protection Lock Register (see protection register and Security Block).
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Table 3. Top Boot Block Addresses, M28W320CT
# 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 Size (KWord) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1FF000-1FFFFF 1FE000-1FEFFF 1FD000-1FDFFF 1FC000-1FCFFF 1FB000-1FBFFF 1FA000-1FAFFF 1F9000-1F9FFF 1F8000-1F8FFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F00000-F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF
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Table 4. Bottom Boot Block Addresses, M28W320CB
# 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F0000-0F7FFF 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 007000-007FFF 006000-006FFF 005000-005FFF 004000-004FFF 003000-003FFF 002000-002FFF 001000-001FFF 000000-000FFF
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SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A20). The address signals are inputs driven with CMOS voltage levels. They are latched during a write operation. Data Input/Output (DQ0-DQ15). The data inputs, a word to be programmed or a command to the C.I., are latched on the Chip Enable E or Write Enable W rising edge, whichever occurs first. The data output from the memory Array, the Electronic Signature, the block protection status or Status Register is valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected, the outputs are disabled or RP is tied to VIL. Commands are issued on DQ0-DQ7. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E at VIH deselects the memory and reduces the power consumption to the stand-by level. E can also be used to control writing to the command register and to the memory array, while W remains at VIL. Output Enable (G). The Output Enable controls the data Input/Output buffers. Write Enable (W). This input controls writing to the Command Register, Input Address and Data latches. Write Protect (WP). This input gives an additional hardware protection level against program or erase when pulled at VIL, as described in the Block Protection description. Reset Input (RP). The RP input provides hardware reset of the memory. When RP is at VIL, the memory is in reset mode: the outputs are put to High-Z and the current consumption is minimised. When RP is at VIH, the device is in normal operation. Exiting reset mode the device enters read array mode. VDD Supply Voltage (2.7V to 3.6V). VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). It ranges from 2.7V to 3.6V. VDDQ Supply Voltage (1.65V to VDD). VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from V DD. VDDQ can be tied to VDD or it can use a separate supply. It can be powered either from 1.65V to VDD. VPP Program Supply Voltage (12V). VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to 3.6V) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions. VPP value is only sampled at the beginning of a program or erase; a change in its value after the operation has been started does not have any effect and program or erase are carried on regularly. If VPP is used in the range 11.4V to 12.6V acts as a power supply pin. In this condition VPP value must be stable until P/E algorithm is completed (see Table 24 and 25). VSS Ground. VSS is the reference for all the voltage measurements.
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DEVICE OPERATIONS Four control pins rule the hardware access to the Flash memory: E, G, W, RP. The following operations can be performed using the appropriate bus cycles: Read, Write the Command of an Instruction, Output Disable, Stand-by, Reset (see Table 5). Read. Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the CFI. Both Chip Enable (E) and Output Enable (G) must be at VIL in order to perform the read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output independently of the device selection. The data read depend on the previous command written to the memory (see instructions RD, RSIG, RSR, RCFI). Read Array is the default state of the device when exiting reset or after power-up. Write. Write operations are used to give Commands to the memory or to latch Input Data to be programmed. A write operation is initiated when Chip Enable E and Write Enable W are at VIL with Output Enable G at VIH. Commands, Input Data Table 5. User Bus Operations
Operation Read Write Output Disable Stand-by Reset E VIL VIL VIL VIH X
(1)
and Addresses are latched on the rising edge of W or E, whichever occur first. Output Disable. The data outputs are high impedance when the Output Enable G is at VIH. Stand-by. Stand-by disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable E is at VIH and the device is in read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable G or Write Enable W inputs. If E switches to VIH during program or erase operation, the device enters in stand-by when finished. Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high impedance. The memory is in Reset mode when RP is at VIL. The power consumption is reduced to the stand-by level, independently from the Chip Enable E, Out-put Enable G or Write Enable W inputs. If RP is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid as it has been compromised by the aborted operation.
G VIL VIH VIH X X
W VIH V IL VIH X X
RP VIH VIH VIH VIH VIL
WP X X X X X
VPP Don't Care VDD or VPPH Don't Care Don't Care Don't Care
DQ0-DQ15 Data Output Data Input Hi-Z Hi-Z Hi-Z
Note: 1. X = VIL or VIH, VPPH = 12V 5%.
Table 6. Read Electronic Signature (RSIG Instruction)
Code Manufact. Code Device Code M28W320CT M28W320CB Device E VIL VIL VIL G VIL VIL VIL W VIH VIH VIH A0 VIL VIH VIH A1 VIL VIL VIL A2-A7 0 0 0 A8-A11 Don't Care Don't Care Don't Care A12-A20 Don't Care Don't Care Don't Care DQ0-DQ7 20h BAh BBh DQ8-DQ15 00h 88h 88h
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Table 7. Read Block Signature (RSIG Instruction)
Block Status Protected Block Unprotected Block Locked Block E VIL VIL VIL G V IL V IL V IL W VIH VIH VIH A0 VIL VIL VIL A1 VIH VIH VIH A2-A7 0 0 0 A8-A11 A12-A20 DQ0 1 0 X (1) DQ1 0 0 1 DQ2-DQ15 00h 00h 00h Don't Care Block Address Don't Care Block Address Don't Care Block Address
Note: 1. A Locked Block can be protected "DQ0 = 1" or unprotected "DQ0 = 0"; see Block protection section.
Table 8. Read Protection Register and Protection Register Lock (RSIG Instruction)
Word Lock Unique Id 0 Unique Id 1 Unique Id 2 Unique Id 3 OTP 0 OTP 1 OTP 2 OTP 3 E VIL VIL VIL VIL VIL VIL VIL VIL VIL G V IL V IL V IL V IL V IL V IL V IL V IL V IL W VIH VIH VIH VIH VIH VIH VIH VIH VIH A0-A7 80h 81h 82h 83h 84h 85h 86h 87h 88h A8-A20 Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care DQ0 0 ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ1 OTP Prot. data ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ2 Security prot. data ID data ID data ID data ID data OTP data OTP data OTP data OTP data DQ3-DQ7 DQ8-DQ15 00h ID data ID data ID data ID data OTP data OTP data OTP data OTP data 00h ID data ID data ID data ID data OTP data OTP data OTP data OTP data
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INSTRUCTIONS AND COMMANDS Sixteen instructions are available (see Tables 9 and 10) to perform Read Memory Array, Read Status Register, Read Electronic Signature, CFI Query, Erase, Program, Double Word Program, Clear Status Register, Program/Erase Suspend, Program/Erase Resume, Block Protect, Block Unprotect, Block Lock and Protection Register Program. Status Register output may be read at any time, during programming or erase, to monitor the progress of the operation. An internal Command Interface (C.I.) decodes the instructions while an internal Program/Erase Controller (P/E.C.) handles all timing and verifies the correct execution of the Program and Erase instructions. P/E.C. provides a Status Register whose bits indicate operation and exit status of the internal algorithms. The Command Interface is reset to Read Array when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequence must be followed exactly. Any invalid combination of commands will reset the device to Read Array. Read (RD) The Read instruction consists of one write cycle (refer to Device Operations section) giving the command FFh. Next read operations will read the addressed location and output the data. When a device reset occurs, the memory is in Read Array as default. Read Status Register (RSR) The Status Register indicates when a program or erase operation is complete and the success or failure of operation itself. Issue a Read Status Register Instruction (70h) to read the Status Register content. The Read Status Register instruction may be issued at any time, also when a Program/ Erase operation is ongoing. The following Read operations output the content of the Status Register. The Status Register is latched on the falling edge of E or G signals, and can be read until E or G returns to VIH. Either E or G must be toggled to update the latched data. Additionally, any read attempt during program or erase operation will automatically output the content of the Status Register. Read Electronic Signature (RSIG) The Read Electronic Signature instruction consists of one write cycle (refer to Device Operations section) giving the command 90h. A subsequent read will output the Manufacturer Code, the Device Code, the Block protection Status, or the Protection Register. See Tables 6, 7 and 8 for the valid address. The Electronic Signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of M28W320C. CFI Query (RCFI) The Common Flash Interface Query mode is entered by writing 98h. Next read operations will read the CFI data. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at this address 81h. This area can be accessed only in read mode and there are no ways of changing the code after it has been written by ST. Write a read instruction to return to Read mode (refer to the Common Flash Interface section). Table 9. Commands
Hex Code 00h 10h 20h 30h 40h 50h 70h 90h or 98h B0h D0h FFh 01h 2Fh C0h 60h Command Invalid/Reserved Alternative Program Set-up Erase Set-up Double Word Program Set-up Program Set-up Clear Status Register Read Status Register Read Electronic Signature, or CFI Query Program/Erase Suspend Program/Erase Resume, Erase Confirm or Unprotect Confirm Read Array Protect Confirm Lock Confirm Protection Program Protection Set-up
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Table 10. Instructions
Mnemonic RD RSR RSIG RCFI EE PG DPG (4) Instruction Read Memory Array Read Status Register Read Electronic Signature Read CFI Erase Program Cycles 1+ 1+ 1+ 1+ 2 2 3 1 1 1st Cycle Operat. Addr. (1) Write Write Write Write Write Write Write Write Write X X X 55h X X X X X Data FFh 70h Operat. Read (2) Read (2) 2nd Cycle Addr. Read Address X Data Data Status Register Data Query D0h Data Input Data Input Operat. 3nd Cycle Addr. Data
Signature 90h or Read (2) 98h Address (3) 98h or Read (2) 90h 20h 40h or 10h 30h 50h B0h Write Write Write CFI Address Block Address Address Address 1
Double Word Program Clear Status CLRS (5) Register Program/ PES Erase Suspend Program/ PER Erase Resume BP BU BL PRP Block Protect Block Unprotect Block Lock Protection Register Program
Write
Address 2
Data Input
1 2 2 2 2
Write Write Write Write Write
X X X X X
D0h 60h 60h 60h C0h Write Write Write Write
Block Address Block Address Block Address Address
01h D0h 2Fh Data Input
Note: 1. X = Don't Care. 2. The first cycle of the RD, RSR, RSIG or RCFI instruction is followed by read operations in the memory array or special register. Any number of read cycle can occur after one command cycle. 3. The signature address recognized are listed in the Tables 6, 7 and 8. 4. Address 1 and Address 2 must be consecutive address differing only for address bit A0. 5. A read cycle after a CLSR instruction will output the memory array.
Erase (EE) Block erasure sets all the bits within the selected block to '1'. One block at a time can be erased. It is not necessary to program the block with 00h as the P/E.C. will do it automatically before erasing. This instruction uses two write cycles. The first command written is the Erase Set up command 20h. The second command is the Erase Confirm command D0h. An address within the block to be erased is given and latched into the memory during the input of the second command. If the second command given is not an erase confirm, the status register bits b4 and b5 are set and the instruction aborts. Read operations output the status register after erasure has started.
Status Register bit b7 returns '0' while the erasure is in progress and '1' when it has completed. After completion the Status Register bit b5 returns '1' if there has been an Erase Failure. Status register bit b1 returns '1' if the user is attempting to program a protected block. Status Register bit b3 returns a '1' if VPP is below VPPLK. Erase aborts if RP turns to VIL. As data integrity cannot be guaranteed when the erase operation is aborted, the erase must be repeated. A Clear Status Register instruction must be issued to reset b1, b3, b4 and b5 of the Status Register. During the execution of the erase by the P/E.C., the memory accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions.
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Table 11. Protection States (1)
Current State (2) (WP, DQ1, DQ0) 100 101 110 111 000 001 011 Program/Erase Allowed yes no yes no yes no no Protect 101 101 111 111 001 001 011 Next State After Event (3) Unprotect 100 100 110 110 000 000 011 Lock 111 111 111 111 011 011 011 WP transition 000 001 011 011 100 101 111 or 110 (4)
Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status. 2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Read Electronic Signature instruction with A1 = VIH and A0 = VIL. 3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed its logic value. 4. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
Table 12. Status Register Bits
Mnemonic Bit Name Logic Level '1' P/ECS 7 P/E.C. Status '0' Erase Suspend Status '1' '0' '1' ES 5 Erase Status '0' PS 4 Program Status '1' '0' '1' VPPS 3 V PP Status '0' Program Suspend Status '1' '0' Erase Success Program Error Program Success VPP Invalid, Abort VPP OK Suspended In Progress or Completed Busy Suspended In progress or Completed Erase Error Definition Ready Note Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits b4 or b5 for Program or Erase Success. On an Erase Suspend instruction P/ECS and ESS bits are set to '1'. ESS bit remains '1' until an Erase Resume instruction is given. ES bit is set to '1' if P/E.C. has applied the maximum number of erase pulses to the block without achieving an erase verify. PS bit set to '1' if the P/E.C. has failed to program a word. VPPS bit is set if the VPP voltage is below VPPLK when a Program or Erase instruction is executed. VPP is sampled only at the beginning of the erase/program operation. On a Program Suspend instruction P/ECS and PSS bits are set to '1'. PSS remains '1' until a Program Resume Instruction is given.
ESS
6
PSS
2
BPS
1
Block Protection Status
'1'
'0' 0 Reserved
Program/Erase on protected Block, BPS bit is set to '1' if a Program or Erase Abort operation has been attempted on a protected block. No operation to protected blocks
Note: Logic level '1' is High, '0' is Low.
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Program (PG) The memory array can be programmed word-byword. This instruction uses two write cycles. The first command written is the Program Set-up command 40h (or 10h). A second write operation latches the Address and the Data to be written and starts the P/E.C. Read operations output the Status Register content after the programming has started. The Status Register bit b7 returns '0' while the programming is in progress and '1' when it has completed. After completion the Status register bit b4 returns '1' if there has been a Program Failure. Status register bit b1 returns '1' if the user is attempting to program a protected block. Status Register bit b3 returns a '1' if VPP is below VPPLK. Programming aborts if RP goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. A Clear Status Register instruction must be issued to reset b4, b3 and b1 of the Status Register. During the execution of the program by the P/E.C., the memory accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions. Double Word Program (DPG) This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempted when VPP is not at VPPH. The operation can also be executed if V PP is below VPPH but result could be uncertain. This instruction uses three write cycles. The first command written is the Double Word Program Set-Up command 30h. A second write operation latches the Address and the Data of the first word to be written, the third write operation latches the Address and the Data of the second word to be written and starts the P/E.C. Read operations output the Status Register content after the programming has started. The Status Register bit b7 returns '0' while the programming is in progress and '1' when it has completed. After completion the Status register bit b4 returns '1' if there has been a Program Failure. Status register bit b1 returns '1' if the user is attempting to program a protected block. Status Register bit b3 returns a '1' if VPP is below VPPLK. Programming aborts if RP goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. A Clear Status Register instruction must be issued to reset b4, b3 and b1 of the Status Register. During the execution of the program by the P/E.C., the memory accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions. Clear Status Register (CLRS) The Clear Status Register uses a single write operation which clears bits b1, b3, b4 and b5 to 0. Its use is necessary before any new operation when an error has been detected. The Clear Status Register is executed writing the command 50h. Program/Erase Suspend (PES) Program/Erase suspend is accepted only during the Program Erase instruction execution. When a Program/Erase Suspend command is written to the C.I., the P/E.C. freezes the Program/Erase operation. Program/Erase Resume (PER) continues the Program/Erase operation. Program/Erase Suspend consists of writing the command B0h without any specific address. The Status Register bit b2 is set to '1' (within 5s) when the program has been suspended. b2 is set to '0' in case the program is completed or in progress. The Status Register bit b6 is set to '1' (within 30s) when the erase has been suspended. b6 is set to '0' in case the erase is completed or in progress. The valid commands while erase is suspended are: Program/Erase Resume, Program, Read Array, Read Status Register, Read Identifier, CFI Query, Block Protect, Block Unprotect, Block Lock and Protection Program. The user can protect the Block being erased issuing the Block Protect, Block Lock or Protection Program commands. In this case the protection status bit will change immediately, but when the erase is resumed, the operation will complete The valid commands while program is suspended are: Program/ Erase Resume, Read Array, Read Status Register, Read Identifier, CFI Query. During program/erase suspend mode, the chip can be placed in a pseudo-stand-by mode by taking E to VIH This reduces active current consumption. Program/Erase is aborted if RP turns to VIL. Program/Erase Resume (PER) If a Program/Erase Suspend instruction was previously executed, the program/erase operation may be resumed by issuing the command D0h. The status register bit b2/b6 is cleared when program/ erase resumes. Read operations output the status register after the program/erase is resumed.
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The suggested flow charts for programs that use the programming, erasure and program/erase suspend/resume features of the memories are shown from Figures 11, 12, 13, 14 and 15. Protection Register Program (PRP) The Protection Register Program uses two write cycles. The first command written is the protection program command C0h. The second write operation latches the Address and the Data to be written to the Protection Register (see Protection Register and Security Block) and start the PE/C. Read operations output the Status Register content after the programming has started. The 64 bits user programmable Segment (85h to 88h) are programmed 16 bits at a time, it can be protected by the user programming bit 1 of the Protection Lock register. The bit 1 of the Protection Lock register protect the bit 2 of the Protection Lock Register. Writing the bit 2 of the Protection Lock Register will result in a permanent protection of the Security Block. Attempting to program a previously protected protection Register will result in a status register error (bit 1 and bit 4 of the status register will be set to '1'). The protection of the Protection Register and/or the Security Block is not reversible. The Protection Register Program cannot be suspended. Block Protect (BP) The BP instruction use two write cycles. The first command written is the protection setup 60h. The second command is block Protect command 01h. The address within the block being protected must be given in order to write the protection state. If the second command is not recognized by the C.I the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of commands. To read the status register write the RSR command. Block Unprotect (BU) The instruction use two write cycles. The first command written is the protection setup 60h. The second command is block Unprotect command d0h. The address within the block being unprotected must be given in order to write the unprotection state. If the second command is not recognized by the C.I the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of commands. To read the status register write the RSR command. Block Lock (BL) The instruction use two write cycles. The first command written is the protection setup 60h. The second command is block Lock command 2Fh. The address within the block being Locked must be given in order to write the Locking state. If the second command is not recognized by the C.I the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of commands. To read the status register write the RSR command.
Table 13. Program, Erase Times and Program/Erase Endurance Cycles (TA = 0 to 70C or -40 to 85C; VDD = 2.7V to 3.6V)
M28W320C Parameter Word Program Double Word Program Main Block Program Test Condition s Min VPP = VDD VPP = 12V 5% VPP = 12V 5% VPP = VDD VPP = 12V 5% Parameter Block Program VPP = VDD VPP = 12V 5% Main Block Erase VPP = VDD VPP = 12V 5% Parameter Block Erase VPP = VDD Program/Erase Cycles (per Block)
Note: TA = 25 C.
Typ (1) 10 10 0.16 0.32 0.02 0.04 1 1 0.8 0.8
Unit Max 200 200 5 5 4 4 10 10 10 10 s s sec sec sec sec sec sec sec sec cycles
100,000
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BLOCK PROTECTION The M28W320C provide a flexible protection of all the memory providing the protection unprotection and locking of any blocks. All blocks are protected at power-up. Each block of the array has two levels of protection against program or erase operation. The first level is set by the Block Protect instruction; a protected block cannot be programmed or erased until a Block Unprotect instruction is given for that block. A second level of protection is set by the Block Lock instruction, and requires the use of the WP pin, according to the following scheme: - when WP is at VIH, the Lock status is overridden and all blocks can be protected or unprotected; - when WP is at VIL, Lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. Blocks that are not locked can still change their protection status; - the lock status is cleared for all blocks at power up. The protection and lock status can be monitored for each block using the Read Electronic Signature (RSIG) instruction. Protected blocks will output a '1' on DQ0 and locked blocks will output a '1' in DQ1. Figure 4. Security Block Memory Map PROTECTION REGISTER and SECURITY BLOCK The M28W320C features a 128-bit protection register and a security Block in order to increase the protection of a system design. The Protection Register is divided in two 64-bit segment. The first segment (81h to 84h) is a unique device number, while the second one (85h to 88h) can be programmed by the user. When shipped the user programmable segment is read at '1'. It can be only programmed at '0'; The user programmable segment can be protected writing the bit 1 of the Protection Lock register (80h). The bit 1 protect also the bit 2 of the Protection Lock Register. The M28W320C feature a security Block. The security Block is located at 1FF000-1FFFFF (M28W320CT) or at 000000000FFF (M28W320CB) of the device. This block can be permanently protected by the user programming the bit 2 of the Protection Lock Register. The protection Register and the Protection Lock Register can be read using the RSIG command. A subsequent read in the address starting from 80h to 88h, the user will retrieve respectively the Protection Lock register, the unique device number segment and the OTP user programmable register segment (see Table 8).
88h User Programmable OTP 85h 84h Parameter Block # 0 81h 80h Protection Register Lock 2 1 0 Unique device number
AI03523
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POWER CONSUMPTION The M28W320C puts itself in one of four different modes depending on the status of the control signals: Active Power, Automatic Stand-by, Stand-by and Reset define decreasing levels of current consumption. These allow the memory power to be minimised, in turn decreasing the overall system power consumption. As different recovery time are linked to the different modes, please refer to the AC timing Table to design your system. Active Power When E is at VIL and RP is at VIH, the device is in active mode. Refer to DC Characteristics to get the values of the current supply consumption. Automatic Stand-by Automatic Stand-by provides a low power consumption state during read mode. Following a read operation, after a delay close to the memory access time, the device enters Automatic Standby: the Supply Current is reduced to ICC1 values. The device keeps the last output data stable, till a new location is accessed. Stand-by or Reset Refer to the Device Operations section. Power Up The Supply voltage VDD and the Program Supply voltage VPP can be applied in any order. The memory Command Interface is reset on power up to Read Memory Array, but a negative transition of Chip Enable E or a change of the addresses is required to ensure valid data outputs. Care must be taken to avoid writes to the memory when VDD is above VLKO. Writes can be inhibited by driving either E or W to VIH. The memory is disabled if RP is at VIL. Supply Rails Normal precautions must be taken for supply voltage decoupling, each device in a system should have the VDD and V PP rails decoupled with a 0.1F capacitor close to the VDD and VPP pins.The PCB trace widths should be sufficient to carry the required V PP program and erase currents.
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COMMON FLASH INTERFACE (CFI) The Common Flash Interface (CFI) specification is a JEDEC approved, standardised data structure that can be read from the Flash memory device. CFI allows a system software to query the flash device to determine various electrical and timing parameters, density information and functions supported by the device. CFI allows the system to easily interface to the Flash memory, to learn about its features and parameters, enabling the software to configure itself when necessary. Tables 14, 15, 16, 17, 18 and 19 show the address used to retrieve each data. Table 14. Query Structure Overview
Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional)
The CFI data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. Tables 14, 15, 16 and 17 show the addresses used to retrieve each data. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 81h. This area can be accessed only in read mode and there are no ways of changing the code after it has been written by ST. Write a read instruction to return to Read mode. Refer to the CFI Query instruction to understand how the M28W320C enters the CFI Query mode.
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 15, 16, 17, 18 and 19. Query data are always presented on the lowest order data outputs.
Table 15. CFI Query Identification String
Offset 00h 01h 02h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0020h 88BAh - top 88BBh - bottom reserved 0051h 0052h 0059h 0003h 0000h offset = P = 0035h Address for Primary Algorithm extended Query table 0000h 0000h 0000h value = A = 0000h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (note: 0000h means none exists) Address for Alternate Algorithm extended Query table note: 0000h means none exists Manufacturer Code Device Code Reserved Query Unique ASCII String "QRY" Query Unique ASCII String "QRY" Query Unique ASCII String "QRY" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Description
Note: Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'.
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Table 16. CFI Query System Interface Information
Offset 1Bh Data 0027h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Note: This value must be 0000h if no VPP pin is present VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Note: This value must be 0000h if no VPP pin is present Typical timeout per single byte/word program (multi-byte program count = 1), 2n s (if supported; 0000h = not supported) Typical timeout for maximum-size multi-byte program or page write, 2n s (if supported; 0000h = not supported) Typical timeout per individual block erase, 2n ms (if supported; 0000h = not supported) Typical timeout for full chip erase, 2n ms (if supported; 0000h = not supported) Maximum timeout for byte/word program, 2n times typical (offset 1Fh) (0000h = not supported) Maximum timeout for multi-byte program or page write, 2n times typical (offset 20h) (0000h = not supported) Maximum timeout per individual block erase, 2n times typical (offset 21h) (0000h = not supported) Maximum timeout for chip erase, 2n times typical (offset 22h) (0000h = not supported)
1Ch
0036h
1Dh
00B4h
1Eh
00C6h
1Fh 20h
0004h 0000h
21h 22h
000Ah 0000h
23h 24h 25h 26h
0004h 0000h 0003h 0000h
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Table 17. Device Geometry Definition
Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch Data 0016h 0001h 0000h 0000h 0000h 0002h Device Size = 2n in number of bytes Flash Device Interface Code description: Asynchronous x16 Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions within device bit 7 to 0 = x = number of Erase Block Regions Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk." 2. x specifies the number of regions within the device containing one or more contiguous Erase Blocks of the same size. For example, a 128KB device (1Mb) having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is considered to have 5 Erase Block Regions. Even though two regions both contain 16KB blocks, the fact that they are not contiguous means they are separate Erase Block Regions. 3. By definition, symmetrically block devices have only one blocking region. M28W320CT 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h M28W320CB 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h M28W320CT Erase Block Region Information 001Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h M28W320CB 0007h 0000h 0020h 0000h 001Eh 0000h 0000h 0001h bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in size. The value z = 0 is used for 128 byte block size. e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase Block Region: e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = "1 block") Note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0 Description
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Table 18. Primary Algorithm-Specific Extended Query Table
Offset (P)h = 35h Data 0050h 0052h 0049h (P+3)h = 38h (P+4)h = 39h (P+5)h = 3Ah 0031h 0030h 0006h 0000h (P+7)h (P+8)h 0000h 0000h Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm bit 0 bit 1 bit 2 bit 3 bit 4 bit 31 to 5 Chip Erase supported (1 = Yes, 0 = No) Erase Suspend supported (1 = Yes, 0 = No) Program Suspend (1 = Yes, 0 = No) Lock/Unlock supported (1 = Yes, 0 = No) Quequed Erase supported (1 = Yes, 0 = No) Reserved; undefined bits are `0' Primary Algorithm extended Query table unique ASCII string "PRI" Description
(P+9)h = 3Eh
0001h
Supported Functions after Suspend Read Array, Read Status Register and CFI Query are always supported during Erase or Program operation bit 0 bit 7 to 1 Program supported after Erase Suspend (1 = Yes, 0 = No) Reserved; undefined bits are `0'
(P+A)h = 3Fh (P+B)h
0000h 0000h
Block Lock Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block Lock Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0'
(P+C)h = 41h
0027h
VDD Logic Supply Optimum Program/Erase voltage (highest performance) bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV
(P+D)h = 42h
00C0h
VPP Supply Optimum Program/Erase voltage bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV
(P+E)h
0000h
Reserved
Table 19. Security Code Area
Offset 80h 81h 82h 83h 84h 85h 86h 87h 88h Data 00XX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 64 bits: User Programmable OTP 64 bits: unique device number Protection Register Lock Description
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Table 20. DC Characteristics (TA = 0 to 70C or -40 to 85C; VDD = VDDQ = 2.7V to 3.6V)
Symbol ILI ILO ICC ICC1 ICC2 Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Stand-by or Automatic Stand-by) Supply Current (Reset) Test Conditio n 0V V IN VDDQ 0V VOUT V DDQ E = VSS, G = VIH, f = 5MHz E = VDDQ 0.2V, RP = VDDQ 0.2V RP = VSS 0.2V Program in progress VPP = 12V 5% Program in progress VPP = VDD Erase in progress VPP = 12V 5% Erase in progress VPP = VDD E = VDDQ 0.2V, Erase suspended VPP > VDD VPP VDD RP = VSS 0.2V Program in progress VPP = 12V 5% Program in progress VPP = VDD Erase in progress VPP = 12V 5% Erase in progress VPP = VDD -0.5 V DDQ 2.7V V DDQ 2.7V IOL = 100A, VDD = VDD min, VDDQ = VDDQ min IOH = -100A, VDD = VDD min, VDDQ = VDDQ min VDDQ -0.1 1.65 11.4 3.6 12.6 1 2 -0.5 V DDQ -0.4 0.7 VDDQ 10 15 15 10 10 5 5 Min Typ Max 1 10 20 50 50 20 20 20 20 50 400 5 5 10 5 10 5 0.4 0.8 VDDQ +0.4 VDDQ +0.4 0.1 Unit A A mA A A mA mA mA mA A A A A mA A mA A V V V V V V V V V V
ICC3
Supply Current (Program)
ICC4
Supply Current (Erase)
ICC5 IPP IPP1 IPP2
Supply Current (Program/Erase Suspend) Program Current (Read or Stand-by) Program Current (Read or Stand-by) Program Current (Reset)
IPP3
Program Current (Program)
IPP4
Program Current (Erase)
VIL VIH VOL VOH V PP1 VPPH VPPLK V LKO
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Program Voltage (Program or Erase operations) Program Voltage (Program or Erase operations) Program Voltage (Program and Erase lock-out) VDD Supply Voltage (Program and Erase lock-out)
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Table 21. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to VDDQ VDDQ/2
1N914
Figure 6. AC Testing Load Circuit
VDDQ/2
3.3k
Figure 5. AC Testing Input Output Waveform
DEVICE UNDER TEST CL = 50pF VDDQ/2 0V
AI00610
OUT
VDDQ
CL includes JIG capacitance
AI00609B
Table 22. Capacitance (1) (TA = 25 C, f = 1 MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
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Table 23. Read AC Characteristics (1) (TA = 0 to 70C or -40 to 85C)
M28W320C 90 Symbol Alt Parameter VDD = 2.7V to 3.6V VDDQ = 2.7V min Min tAVAV tAVQV tAXQX (2) tEHQX (2) tEHQZ (2) tELQV (3) tELQX (2) tGHQX (2) tGHQZ (2) tGLQV (3) tGLQX (2) tPHQV tPLPH (2,4)
Note: 1. 2. 3. 4.
100 V DD = 2.7V to 3.6V VDDQ = 1.65V min Min 100 90 100 0 0 25 90 30 100 0 0 25 30 30 35 0 150 150 100 Max
Unit
Max
tRC tACC tOH tOH tHZ tCE tLZ tOH tDF tOE tOLZ tPWH tRP
Address Valid to Next Address Valid Address Valid to Output Valid Address Transition to Output Transition Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Reset High to Output Valid Reset Pulse Width
90
ns ns ns ns ns ns ns ns ns ns ns ns ns
0 0
0 0
0
100
See AC Testing Measurement conditions for timing measurements. Sampled only, not 100% tested. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. The device Reset is possible but not guaranteed if tPLPH < 100ns.
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tAVAV VALID tAVQV tAXQX
Figure 7. Read AC Waveforms
A0-A20
E tELQV tELQX tEHQX tEHQZ
G tGLQV tGLQX VALID tPHQV tGHQX tGHQZ
DQ0-DQ15
RP ADDRESS VALID AND CHIP ENABLE OUTPUTS ENABLED DATA VALID STANDBY
POWER-UP AND STANDBY
AI02688
M28W320CT, M28W320CB
Note: Write Enable (W) = High.
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Table 24. Write AC Characteristics, Write Enable Controlled (1) (TA = 0 to 70C or -40 to 85C)
M28W320C 90 Symbol Alt Parameter VDD = 2.7V to 3.6V VDDQ = 2.7V min Min tAVAV tAVWH tDVWH tELWL tPHWL tPLPH (2, 3) tPLRH (2, 4) tQVVPL (2, 5) tQVWPL t VPHWH (2) tWHAX tWHDX tWHEH tWHGL tWHWL tWLWH tWPHWH tAVAV tAVWH
Note: 1. 2. 3. 4. 5.
100 VDD = 2.7V to 3.6V VDDQ = 1.65V min Min 100 50 50 0 100 100 30 30 0 0 200 0 0 0 30 30 50 50 100 50 Max ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns Unit
Max
tWC tAS tDS tCS tPS tRP
Write Cycle Time Address Valid to Write Enable High Data Valid to Write Enable High Chip Enable Low to Write Enable Low Reset High to Write Enable Low Reset Pulse Width Reset Low to Program/Erase Abort Output Valid to VPP Low Data Valid to Write Protect Low
90 50 50 0 90 100
0 0 200 0 0 0 30 30 50 50 90 50
tVPS tAH tDH tCH
VPP High to Write Enable High Write Enable High to Address Transition Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Output Enable Low
tWPH tWP
Write Enable High to Write Enable Low Write Enable Low to Write Enable High Write Protect High to Write Enable High
tWC tAS
Write Cycle Time Address Valid to Write Enable High
See AC Testing Measurement conditions for timing measurements. Sampled only, not 100% tested. The device Reset is possible but not guaranteed if tPLPH < 100ns. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase mode. Applicable if VPP is seen as a logic input (VPP < 3.6V).
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PROGRAM OR ERASE tAVAV VALID tAVWH tWHAX
A0-A20
E tWHEH
tELWL
G tWHWL tWHGL
W tWLWH tWHQV tWHDX COMMAND CMD or DATA STATUS REGISTER
Figure 8. Write AC Waveforms, W Controlled
tDVWH
DQ0-DQ15
tPHWL
RP
tWPHWH
tQVWPL
WP
tVPHWH
tQVVPL
VPP
POWER-UP AND SET-UP COMMAND
CONFIRM COMMAND OR DATA INPUT
STATUS REGISTER READ 1st POLLING
AI03574
M28W320CT, M28W320CB
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Table 25. Write AC Characteristics, Chip Enable Controlled (1) (TA = 0 to 70C or -40 to 85C)
M28W320C 90 Symbol Alt Parameter 100 Unit
V DD = 2.7V to 3.6V VDD = 2.7V to 3.6V V DDQ = 2.7V min VDDQ = 1.65V min Min Max Min 100 50 50 0 0 30 30 0 50 100 100 30 0 0 200 0 50 90 50 0 0 200 0 50 100 50 30 Max
tAVAV tAVEH tDVEH t EHAX tEHDX tEHEL t EHGL tEHWH tELEH tPHEL tPLPH (2, 3) tPLRH (2, 4) t QVVPL (2, 5) tQVWPL tVPHEH (2) t WLEL tWPHEH tAVAV tAVEH
Note: 1. 2. 3. 4. 5.
tWC tAS tDS tAH tDH tCPH
Write Cycle Time Address Valid to Chip Enable High Data Valid to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Data Transition Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low
90 50 50 0 0 30 30 0 50 90 100
ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns
tWH tCP tPS tRP
Chip Enable High to Write Enable High Chip Enable Low to Chip Enable High Reset High to Chip Enable Low Reset Pulse Width Reset Low to Program/Erase Abort Output Valid to VPP Low Data Valid to Write Protect Low
tVPS tCS
VPP High to Chip Enable High Write Enable Low to Chip Enable Low Write Protect High to Chip Enable High
tWC tAS
Write Cycle Time Address Valid to Chip Enable High
See AC Testing Measurement conditions for timing measurements. Sampled only, not 100% tested. The device Reset is possible but not guaranteed if tPLPH < 100ns. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase mode. Applicable if VPP is seen as a logic input (VPP < 3.6V).
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PROGRAM OR ERASE tAVAV VALID tAVEH tEHAX
A0-A20
W tEHWH
tWLEL
G tEHEL tEHGL
E tELEH tEHDX COMMAND CMD or DATA STATUS REGISTER tEHQV
Figure 9. Write AC Waveforms, E Controlled
tDVEH
DQ0-DQ15
tPHEL
RP tWPHEH tQVWPL
WP
tVPHEH
tQVVPL
VPP
POWER-UP AND SET-UP COMMAND
CONFIRM COMMAND OR DATA INPUT
STATUS REGISTER READ 1st POLLING
AI03575
M28W320CT, M28W320CB
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Figure 10. Reset AC Waveform
Reset during Read Mode tPLPH RP tPHQV
Reset during Program with tPLPH tPLRH Abort Complete tPLRH tPLPH RP
tPHWL tPHEL
Reset during Program/Erase with tPLPH > tPLRH Abort Complete Reset tPLRH tPLPH RP
AI03537
tPHWL tPHEL
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Figure 11. Program Flowchart and Pseudo Code
Start
Write 40h or 10h Command
Write Address & Data
Program instruction: - write 40h or 10h command - write Address & Data (memory enters read status state after the Program instruction)
NO Read Status Register Suspend NO YES Suspend Loop
do: - read status register (E or G must be toggled) if PES instruction given execute suspend program loop
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
while b7 = 1 NO
VPP Invalid Error (1, 2)
If b3 = 1, VPP invalid error: - error handler
NO
Program Error (1, 2)
If b4 = 1, Program error: - error handler
NO
Program to Protected Block Error (1, 2)
If b1 = 1, Program to protected block error: - error handler
AI03538
Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
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M28W320CT, M28W320CB
Figure 12. Double Word Program Flowchart and Pseudo Code
Start
Write 30h Command
Write Address 1 & Data 1 (3)
DPG instruction: - write 30h command - write Address 1 & Data 1 (3) - write Address 2 & Data 2 (3) (memory enters read status state after the Program instruction)
Write Address 2 & Data 2 (3)
NO Read Status Register Suspend NO YES Suspend Loop
do: - read status register (E or G must be toggled) if PES instruction given execute DPG suspend loop
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
while b7 = 1 NO VPP Invalid Error (1, 2) If b3 = 1, VPP invalid error: - error handler
NO
Program Error (1, 2)
If b4 = 1, Program error: - error handler
NO
Program to Protected Block Error (1, 2)
If b1 = 1, Program to protected block error: - error handler
AI03539
Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for address bit A0.
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M28W320CT, M28W320CB
Figure 13. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h Command
Write 70h Command
PES instruction: - write B0h command do: - read status register (E or G must be toggled)
Read Status Register
b7 = 1 YES b2 = 1 YES Write a read Command
NO
while b7 = 1
NO
Program Complete
If b2 = 0 Program completed
Read data from another address PER instruction: - write D0h command to resume the program - if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued).
Write D0h Command
Write FFh Command
Program Continues
Read Data
AI03540
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M28W320CT, M28W320CB
Figure 14. Erase Flowchart and Pseudo Code
Start
Write 20h Command
Write Block Address & D0h Command
EE instruction: - write 20h command - write Block Address (A12-A20) & command D0h (memory enters read status state after the EE instruction) do: - read status register (E or G must be toggled) if PES instruction given execute suspend erase loop YES
Read Status Register
NO Suspend
b7 = 1
NO
Suspend Loop while b7 = 1
YES b3 = 0 YES b4, b5 = 0 YES b5 = 0 YES b1 = 0 YES End NO Erase to Protected Block Error (1) NO Erase Error (1) NO Command Sequence Error (1) NO VPP Invalid Error (1)
If b3 = 1, VPP invalid error: - error handler
If b4, b5 = 1, Command sequence error: - error handler
If b5 = 1, Erase error: - error handler
If b1 = 1, Erase to protected block error: - error handler
AI03541
Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
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M28W320CT, M28W320CB
Figure 15. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h Command
Write 70h Command
PES instruction: - write B0h command do: - read status register (E or G must be toggled)
Read Status Register
b7 = 1 YES b6 = 1 YES
NO
while b7 = 1
NO
Erase Complete
If b6 = 0, Erase completed
Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock
Write D0h Command
Write FFh Command
Erase Continues
Read Data
PER instruction: - write D0h command to resume erasure - if the erase operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued).
AI03542
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M28W320CT, M28W320CB
Figure 16. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR COMMAND WRITE (1)
90h YES READ SIGNATURE
NO
98h YES CFI QUERY
NO
70h YES READ STATUS
NO
50h YES CLEAR STATUS
NO
60h YES BP/BU/BL SET-UP
NO
C0h YES
NO
D READ STATUS
PRP SET-UP
40h or 10h YES
NO
READ ARRAY
YES
READY (2)
PRP
PROGRAM SET-UP C
30h YES
NO
B
NO
DPG SET-UP C
20h YES ERASE SET-UP
NO
B
01h YES BLOCK PROTECT
NO
D0h YES
NO
2Fh YES
NO
BP/BU/BL COMMAND ERROR
FFh YES
NO
D0h BLOCK UNPROTECT BLOCK LOCK A YES
NO
ERASE COMMAND ERROR
AI03543
Note: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or if VDD falls below V LKO, the Command Interface defaults to Read Array mode. 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
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M28W320CT, M28W320CB
Figure 17. Command Interface and Program Erase Controller Flowchart (b)
A
B
ERASE
(READ STATUS)
YES
READY (2) NO NO
ERASE NO SUSPENDED
B0h YES
YES ERASE SUSPEND READ STATUS YES 70h NO READ SIGNATURE YES YES READY (2) NO READ STATUS
READ STATUS
90h NO
CFI QUERY
YES
98h NO
PROGRAM SET-UP c DPG SET-UP c
YES
40h or 10h NO
YES
30h NO YES PRP SET-UP PRP READY (2) NO YES
C0h NO BP/BU/BL SET-UP D READ ARRAY NO YES
B
60h NO YES ERASE RESUME (READ STATUS)
D0h
AI03544
Note: 2. P/E. C. status (Ready or Busy) is read on Status Register bit 7.
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M28W320CT, M28W320CB
Figure 18. Command Interface and Program Erase Controller Flowchart (c)
B
C
PROGRAM
(READ STATUS)
YES
READY (2) NO NO
B0h YES
READ STATUS PROGRAM SUSPEND NO PROGRAM SUSPENDED YES YES READY (2) NO READ STATUS YES READ STATUS
70h NO
READ SIGNATURE
YES
90h NO
CFI QUERY
YES
98h NO
READ ARRAY
NO
D0h
YES
PROGRAM RESUME
(READ STATUS)
AI03545
Note: 2. P/E. C. status (Ready or Busy) is read on Status Register bit 7.
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M28W320CT, M28W320CB
Table 26. Ordering Information Scheme
Example: Device Type M28 Operating Voltage W = VDD = 2.7V to 3.6V; V DDQ = 1.65V or 2.7V Device Function 320C = 32 Mbit (2 Mb x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot Random Speed 90 = 90 ns 100 = 100 ns Package N = TSOP48: 12 x 20 mm GB = BGA47: 0.75 mm pitch Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Optio n T = Tape & Reel Packing M28W320CT 90 N 6 T
Devices are shipped from the factory with the memory content bits erased to '1'. Table 27. Daisy Chain Ordering Scheme
Example: Device Type M28W320C Daisy Chain -GB = BGA47: 0.75 mm pitch Optio n T = Tape & Reel Packing M28W320C -GB T
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M28W320CT, M28W320CB
Table 28. Revision History
Date February 2000 04/19/00 05/17/00 First Issue Daisy Chain part numbering defined BGA Package Outline diagram change (Figure 20) BGA Chain diagrams, Package and PCB Connection re-designed (Figure 21, 22) BGA Package Outline diagram and Package Mechanical Data change (Figure 20, Table 30) Revision Details
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M28W320CT, M28W320CB
Table 29. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 11.90 - 0.50 0 48 0.10 Min Max 1.20 0.15 1.05 0.27 0.21 20.20 18.50 12.10 - 0.70 5 0.0197 0.0020 0.0374 0.0067 0.0039 0.7795 0.7205 0.4685 - 0.0197 0 48 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.7953 0.7283 0.4764 - 0.0276 5 inches
Figure 19. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Drawing is not to scale.
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M28W320CT, M28W320CB
Table 30. BGA47 - 8 x 6 balls, 0.75 mm pitch, Package Mechanical Data
mm Symbol Typ A A1 A2 b D D1 ddd e E E1 FD FE 0.750 6.390 5.250 3.375 0.570 - 6.340 - - - 0.700 0.350 10.500 3.750 0.180 - 0.300 10.450 - - 0.400 10.550 - 0.080 - 6.440 - - - 0.0295 0.2516 0.2067 0.1329 0.0224 - 0.2496 - - - 0.0276 0.0138 0.4134 0.1476 Min Max 1.000 0.0071 - 0.0118 0.4114 - - 0.0157 0.4154 - 0.0031 - 0.2535 - - - Typ Min Max 0.0394 inch
Figure 20. BGA47 - 8 x 6 balls, 0.75 mm pitch, Bottom View Package Outline
E E1 FE SE
FD
SD D D1
BALL "A1"
e ddd e b A2 A1
A
BGA-G06
Drawing is not to scale. 40/42
M28W320CT, M28W320CB
Figure 21. BGA47 Daisy Chain - Package Connections (Top view through package)
1 2 3 4 5 6 7 8
A
B
C
D
E
F
AI03295
Figure 22. BGA47 Daisy Chain - PCB Connections (Top view through package)
1 2 3 4 5 6 7 8
A
START POINT
B
C
D
E
F
END POINT
AI3296
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M28W320CT, M28W320CB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . http://w ww.st.com
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